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SEMICONDUCTOR TECHNICAL DATA
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Designer'sTM Data Sheet
TMOS E-FET.TM Power Field Effect Transistor TO-247 with Isolated Mounting Hole
N-Channel Enhancement-Mode Silicon Gate
This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage-blocking capability without degrading performance over time. In addition, this advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. * Robust High Voltage Termination * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Isolated Mounting Hole Reduces Mounting Hardware MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage -- Continuous Gate-Source Voltage -- Non-Repetitive (tp 10 ms) Drain Current -- Continuous Drain Current -- Continuous @ 100C Drain Current -- Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 10 mH, RG = 25 ) Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS RJC RJA TL G S
MTW20N50E
Motorola Preferred Device
TMOS POWER FET 20 AMPERES 500 VOLTS RDS(on) = 0.24 OHM
(R)
D
CASE 340K-01, Style 1 TO-247AE
Value 500 500 20 40 20 14.1 60 250 2.0 - 55 to 150 2000 0.50 40 260
Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C C mJ C/W C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
E-FET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4
(c)Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1996
1
MTW20N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 500 Vdc, VGS = 0 Vdc) (VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 10 Adc) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 400 Vdc, ID = 20 Adc, Vd Ad VGS = 10 Vdc) Adc, (VDD = 250 Vdc, ID = 20 Ad Vd VGS = 10 Vdc Vdc, RG = 9.1 ) ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (1) (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125C) VSD -- -- trr ( (IS = 20 Adc, VGS = 0 Vdc, Ad , Vd , dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. LD LS -- -- 5.0 13 -- -- nH nH ta tb QRR -- -- -- -- 0.916 0.81 431 272 159 6.67 1.1 -- -- -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 29 90 97 84 100 20 44 36 55 165 190 170 132 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vdc Vdc f = 1.0 MHz) Ciss Coss Crss -- -- -- 3880 452 96 6950 920 140 pF VGS(th) 2.0 -- RDS(on) VDS(on) -- -- gFS 11 5.75 -- 16.2 6.0 6.0 -- mhos -- 3.0 7.0 0.20 4.0 -- 0.24 Vdc mV/C Ohm Vdc V(BR)DSS 500 -- IDSS -- -- IGSS -- -- -- -- 10 100 100 nAdc -- 583 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
Reverse Recovery Time (See Figure 14)
2
Motorola TMOS Power MOSFET Transistor Device Data
MTW20N50E
TYPICAL ELECTRICAL CHARACTERISTICS
40 TJ = 25C I D , DRAIN CURRENT (AMPS) 32 VGS = 10 V 9V 8V I D , DRAIN CURRENT (AMPS) 32 40 VDS 10 V
24
7V
24
16 6V 8 5V 0 0 2 6 10 14 18 4 8 12 16 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 20
16
100C 25C TJ = - 55C
8
0 2.0 2.4
2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
6.4
6.8
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.6 VGS = 10 V 0.5 0.4 0.3 0.2 - 55C 0.1 0 0 4 8 12 20 28 16 24 ID, DRAIN CURRENT (AMPS) 32 36 40 25C TJ = 100C
0.34 TJ = 25C 0.32
0.30 VGS = 10 V
0.28
0.26
15 V
0.24 0 4 8 16 24 12 20 28 ID, DRAIN CURRENT (AMPS) 32 36 40
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2.4 2.0 1.6 1.2 0.8 0.4 0 - 50 VGS = 10 V ID = 10 A
10000 VGS = 0 V TJ = 125C I DSS , LEAKAGE (nA) 1000 100C
100
10 25C 1 - 25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 150 0 50 100 150 200 250 300 350 400 450 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 500
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTW20N50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
9000 8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 10 5 VGS Crss Ciss VDS = 0 V Ciss C, CAPACITANCE (pF) VGS = 0 V TJ = 25C
10000 VGS = 0 V Ciss 1000 TJ = 25C
100
Coss
Crss Crss 0 VDS 5 10 Coss 15 20 25 10 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
Figure 7b. High Voltage Capacitance Variation
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Motorola TMOS Power MOSFET Transistor Device Data
MTW20N50E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 QT 8 Q1 6 Q2 300 VGS 400 500 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 VDD = 250 V ID = 20 A VGS = 10 V TJ = 25C t, TIME (ns) td(off) tr tf
100 td(on)
4 ID = 20 A TJ = 25C Q3 0 0 10 20 30 40 50 60 70 QG, TOTAL GATE CHARGE (nC) VDS 80 90
200
2
100
0 100
10 1 10 RG, GATE RESISTANCE (OHMS) 100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
20 I S , SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25C
16
12
8
4
0 0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82 0.86 0.90 0.94 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
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MTW20N50E
SAFE OPERATING AREA
VGS = 20 V SINGLE PULSE TC = 25C 100 s 1.0 1 ms 10 ms dc 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 10 1.0 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) 100 10 s 2000 1800 1600 1400 1200 1000 800 600 400 200 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 ID = 20 A
I D , DRAIN CURRENT (AMPS)
10
0.01
Figure 11. Maximum Rated Forward Biased Safe Operating Area
1.0 D = 0.5 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 1.0E-05 P(pk)
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01
t1
RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t)
1.0E-04
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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Motorola TMOS Power MOSFET Transistor Device Data
MTW20N50E
PACKAGE DIMENSIONS
0.25 (0.010)
M
-Q- TBM
-T- E -B- U L R
1 2 3
C
4
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX 19.7 20.3 15.3 15.9 4.7 5.3 1.0 1.4 1.27 REF 2.0 2.4 5.5 BSC 2.2 2.6 0.4 0.8 14.2 14.8 5.5 NOM 3.7 4.3 3.55 3.65 5.0 NOM 5.5 BSC 3.0 3.4 INCHES MIN MAX 0.776 0.799 0.602 0.626 0.185 0.209 0.039 0.055 0.050 REF 0.079 0.094 0.216 BSC 0.087 0.102 0.016 0.031 0.559 0.583 0.217 NOM 0.146 0.169 0.140 0.144 0.197 NOM 0.217 BSC 0.118 0.134
A
K
P
-Y-
V F D 0.25 (0.010)
M
H J
G
DIM A B C D E F G H J K L P Q R U V STYLE 1: PIN 1. 2. 3. 4.
YQ
S GATE DRAIN SOURCE DRAIN
CASE 340K-01 ISSUE O
Motorola TMOS Power MOSFET Transistor Device Data
7
MTW20N50E
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Motorola TMOS Power MOSFET TransistorMTW20N50E/D Device Data
*MTW20N50E/D*

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